In one embodiment, a parameter, when applied to analog standard cells, could be used generally to mean any parameter or feature that may alter some property of the cell. The general type analog standard cell could be a family of cells that may implement NMOS and PMOS transistors of differing parameters. 6 b) and an exemplary pass gate (as shown in FIG. Thus, these non-general analog standard cell examples will not be detailed further, with the exception of a brief layout-level description of an exemplary differential pair (as shown in FIG. With the exception of the general type, which will be described shortly, the names of these exemplary types of analog standard cells imply corresponding analog functions and physical layouts that are well-known in the art.

Examples of analog standard cell types of a library may include, but are not limited to, general types, differential pairs, moscaps, varactors, resistors, current sources, current mirrors, well-taps, and ESD devices. Generally, a library containing more types of analog standard cells, and with more parametric variations of a particular type of analog standard cell, has greater utility. The utility of an analog standard cell library may be defined in part by the ability, efficiency, and speed that an ECAD tool can select, place, and route analog standard cells from such library to design an analog or mixed-signal SoC. This orders-of-magnitude productivity gap is the direct result of decades of advancements made in the place-and-route efficiency of ECAD tools. Whereas digital designer productivity is currently measured in millions of transistors placed per day, state-of-the-art analog designer productivity is currently measured in only tens of transistors per day. A billion-transistor SoC design may be laid out using this ECAD-based standard cell methodology within a few months. Modern ECAD tools are very efficient in place and route operations, which has resulted in an enormous productivity boost in the physical design flow of digital SoCs.

Placement refers to the physical positioning of a standard cell within an SoC layout and routing refers to the determination of conductive interconnects between such cells. ECAD tools generally place and route standard cells based on some predefined constraints, such as the timing of electrical signals between standard cells or minimization of layout area. ECAD tools are used to select standard cells from a library, map the circuitry of an SoC design to standard cells, place standard cells, and route (interconnect) standard cells to create the physical design (the layout).

311 transistor b sides